1. Field of the Invention
The present invention relates to a method of fabricating a multi-layer circuit board, and more particularly, to a method of fabricating a multi-layer circuit board with fine pitches.
2. Description of the Prior Art
In the past, various build-up layer methods of high-density IC package substrates and printed circuit boards for achieving finer pitch and multiple layers have been disclosed, including laminations of dielectric films, resin-coated copper (RCC), and prepreg.
Recently, a more advanced build-up method has been introduced by providing an insulating core layer with completed upper circuit layers and lower circuit layers, in which the upper and lower circuit layers are electrically connected. To establish the connection between the upper and lower circuit layers, a plurality of plated though holes (PTH) is formed in the core layer to connect upper and lower circuit layers. Next, a laminating process is utilized to form a dielectric layer onto the core layer and form a plurality of vias by laser drilling on the dielectric layer to expose the contact pads of circuit layers. Next, a conductive seed layer is formed over the surface of the dielectric layer, and then utilizing a photolithography process to form patterned photoresist layer with recesses to expose the vias. Fabricating an electroplating process, a conductive material is formed into the via and the recess of patterned photoresist layer, and then removing the photoresist layer and the exposed conductive seed layer under photoresist layer, a build-up circuit layer is formed and the entire fabrication process is referred to as a semi additive process (SAP).
In general, packaging substrates and printed circuit boards that utilize the SAP methods are able to achieve precise fine pitches with line-width/line-space (L/S) of 20 μm/20 μm, in which the shape of the lines are able to obtain good resistance control and electrical properties. Eventually, the build-up method can be applied to various higher-level printed circuit boards such as flip chip IC packaging substrate.
Nevertheless, numerous difficulties with this technique are yet to be solved as is evident by the various disadvantages that still exist with SAP fabrication. One disadvantage occurs as the lines get finer, such as reaching a L/S of 10 μm/10 μm. At this point the integration of conductive lines and dielectric layers unavoidably becomes much worse, thereby causing problems such as cracks or delaminations. Additionally, as the circuit layout get into fine pitches, the photomasks utilized during fabrication processes are easily trapped within the space between each line, thereby affecting the quality and electrical property of the product. Moreover, the etching process utilized during standard SAP processes for removing the conductive seed layer influences the precision of the shape and size (line width) of the fine lines.